Advanced Semiconductor Substrates for High-Efficiency Photovoltaic Devices

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The growth of high-quality, single-crystalline Ge on Si substrates offers promising avenues for fabricating high-efficiency multijunction solar cells, among other things, such as infrared sensors and light emitters. The figure below shows an example device architecture for triple-junction solar cells.  Here, III-V materials (e.g., GaInP2 and GaAs) are grown on top of Ge, and each layer captures different portion of the sunlight spectrum to harness as much of the sunlight as possible and increase the overall photoelectric conversion efficiency.  An efficiency as high as 39% is achievable today from multijunction solar cells.  The high efficiency, however, comes at a cost as these multijunction solar cells are typically manufactured on expensive Ge substrates, whose price constitutes over 50% of the manufacturing cost.  Thus, replacing Ge wafers with less expensive, lighter weight, mechanically stronger Si wafers is an ideal solution to reduce the manufacturing cost.

The solution proposed above requires growing high-quality Ge on Si.  Despite the significant improvement made over the past two decades, however, the 4.2% lattice mismatch between Ge and Si generally leads to a high density of threading dislocations, which adversely reduce the film and device quality.  One highly promising approach to reduce the impact of lattice mismatch is known as selective epitaxial growth (SEG), shown schematically below.

Figure: Strain density at the Ge-Si heterojunction decreases rapidly as a function of decreasing Ge-Si junction size. The graded red color scheme represents the strain decay from the Ge-Si heterojunction. Note that the Ge growing laterally above SiO2 is not registered with Si.

Figure: Strain density at the Ge-Si heterojunction decreases rapidly as a function of decreasing Ge-Si junction size. The graded red color scheme represents the strain decay from the Ge-Si heterojunction. Note that the Ge growing laterally above SiO2 is not registered with Si.

The SEG process applies a templated interlayer to significantly reduce the strain energy density at the mismatched heterojunction and/or to trap defects from propagating.  In a typical SEG process, a thin interlayer (most commonly comprised of SiO2) that provides separation between Ge and Si is deposited on a Si substrate and subsequently perforated using one of several possible approaches.  The Si exposed by the perforations serves as seeding sites (or “pads”) for the growth of crystalline Ge islands.  These islands grow and coalesce, forming a high-quality (but not perfect) Ge film.

While the decreasing Ge-Si contact area reduces the strain density near the heterojunction, island-island coalescence unavoidably leads to defects such as dislocations and grain boundaries.  The mechanism for this defect formation is still not yet understood and is the focus of our simulation work in this area.  We are employing large-scale molecular dynamics simulations to examine the formation of defects during SEG.  In order to accommodate the large numbers of atoms required to study this process, we use empirical potential models to characterize the interactions between amorphous SiO2 layer, silicon, and germanium.  However, empirical potential functions for the Si-Ge-O ternary system are not currently well-tested and we are using detailed experimental data to validate them.

An example point-of-contact between atomistic simulations and the experimental data provided by collaborators at the University of New Mexico is shown in the figure below.  The images on the left are electron microscopy images of germanium islands on amorphous silicon dioxide annealed at different temperatures.  The simulation images on the right show the morphological evolution of a germanium nanosphere on an amorphous silica substrate.

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(Project is in collaboration with Prof S. Han at the University of New Mexico.)